1. Field of the Invention
The present invention relates to semiconductor storage devices, and particularly to the structure of a semiconductor storage device having SRAM (Static Random Access Memory) memory cells.
2. Description of the Background Art
FIG. 24 is a circuit diagram showing the structure of a conventional SRAM memory cell. The NMOS transistors Q1 and Q4 are transistors for driving (referred to also as xe2x80x9cdriver transistorsxe2x80x9d) and the NMOS transistors Q3 and Q6 are transistors for accessing (referred to also as xe2x80x9caccess transistorsxe2x80x9d). The PMOS transistors Q2 and Q5 are transistors for load (load transistors); the PMOS transistors Q2 and Q5 may be replaced by resistor elements.
The NMOS transistors Q1 and Q4 have their respective sources connected to a power supply 2 which gives a GND potential. The PMOS transistors Q2 and Q5 have their respective sources connected to a power supply 1 which gives a given power-supply potential (Vdd). The NMOS transistor Q1 and the PMOS transistor Q2 have their respective drains connected to a storage node ND1. The NMOS transistor Q4 and the PMOS transistor Q5 have their respective drains connected to a storage node ND2. The storage node ND1 is connected to the gates of the NMOS transistor Q4 and the PMOS transistor Q5. The storage node ND2 is connected to the gates of the NMOS transistor Q1 and the PMOS transistor Q2. The NMOS transistor Q3 has its gate connected to a word line WL, its source connected to the storage node ND1, and its drain connected to a bit line BL0. The NMOS transistor Q6 has its gate connected to the word line WL, its source connected to the storage node ND2, and its drain connected to a bit line BL1.
FIG. 25 is a top view schematically showing the structure of the conventional SRAM memory cell. Element isolation insulating film 4 is partially formed on a silicon substrate to define element formation regions. The NMOS transistor Q1 shown in FIG. 24 has a source region 5 and a drain region 6, both of which are n+ type. The PMOS transistor Q2 has a source region 8 and a drain region 9, both of which are p+ type. The NMOS transistor Q4 has a source region 10 and a drain region 11, both of which are n+ type. The PMOS transistor Q5 has a source region 13 and a drain region 14, both of which are p+ type. The NMOS transistor Q3 has a source region 6 and a drain region 15, both of which are n+ type, and the NMOS transistor Q6 has a source region 11 and a drain region 16, both of which are n+ type.
The NMOS transistor Q1 and the PMOS transistor Q2 have a common gate structure 7, the gate structure 7 being connected to the drain regions 11 and 14 of the NMOS transistor Q4 and the PMOS transistor Q5. The NMOS transistor Q4 and the PMOS transistor Q5 have a common gate structure 12, the gate structure 12 being connected to the drain regions 6 and 9 of the NMOS transistor Q1 and the PMOS transistor Q2. The NMOS transistors Q3 and Q6 have a common gate structure 17, which functions as the word line WL.
The conventional semiconductor storage device thus constructed is prone to a phenomenon (soft error) in which stored information is upset when ionizing radiation, such as alpha (xcex1) rays emitted from the package material etc., enters the memory cells.
For example, referring to FIG. 24, suppose that the potential at the storage node ND1 is at a high level and the potential at the storage node ND2 is at a low level. Under this condition, when an alpha-ray is incident in the drain of the NMOS transistor Q1, the alpha-radiation generates a large number of electron-hole pairs and the electrons are collected by the drain of the NMOS transistor Q1, which causes the potential at the storage node ND1 to change from the high level to the low level. The potential change at the storage node ND1 is then transferred to the NMOS transistor Q4 and the PMOS transistor Q5, causing the potential at the storage node ND2 to change from the low level to the high level. The potential change at the storage node ND2 is then transferred to the NMOS transistor Q1 and the PMOS transistor Q2. The information stored in the semiconductor storage device is thus destroyed.
An object of the present invention is to obtain a semiconductor storage device having high soft-error immunity.
According to a first aspect of the present invention, a semiconductor storage device includes a static random access memory cell which includes a first driver transistor, a first load element, and a first access transistor which are connected to each other through a first storage node, and a second driver transistor, a second load element, and a second access transistor which are connected to each other through a second storage node, the first driver transistor having a first gate electrode connected to the second storage node, the second driver transistor having a second gate electrode connected to the first storage node. The semiconductor storage device further includes a first protection film formed to cover part of the first gate electrode. Part of the first gate electrode which is not covered by the first protection film has a structure in which a first semiconductor layer and a first metal-semiconductor compound layer are stacked in this order on a first gate insulating film. The part of the first gate electrode which is covered by the first protection film has a structure in which the first semiconductor layer is formed on the first gate insulating film and the first metal-semiconductor compound layer is not formed on the first semiconductor layer.
The second storage node is connected to the first driver transistor through a high resistance portion of the first gate electrode which is covered by the first protection film and where the first metal-semiconductor compound layer is absent. This enhances the soft-error immunity of the semiconductor storage device.
According to a second aspect of the invention, another semiconductor storage device includes a static random access memory cell which includes a first driver transistor, a first load element, and a first access transistor which are connected to each other through a first storage node, and a second driver transistor, a second load element, and a second access transistor which are connected to each other through a second storage node, the first driver transistor having a first gate electrode connected to the second storage node, the second driver transistor having a second gate electrode connected to the first storage node. The semiconductor storage device further includes a first resistance-adding transistor having a first impurity-containing region connected to the first gate electrode and a second impurity-containing region connected to the second storage node, and the first gate electrode is connected to the second storage node through the first resistance-adding transistor.
The first gate electrode is connected to the second storage node through the first resistance-adding transistor, which enhances the soft-error immunity of the semiconductor storage device.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.